The present invention relates generally to solar cells and, more particularly, to improvements in solar cells having by-pass diodes for preventing the solar cells from being damaged when a reverse bias voltage is applied to the solar cells.
Referring to FIG. 1, there is schematically illustrated one example of a typical electric power generating device utilizing sunlight. This electric power generating device includes a solar cell array having a plurality of solar cells arranged in a matrix. The cell array includes a plurality of submodules 30 which are electrically connected in series, and each of the submodules 30 includes a plurality of solar cells 10, 11, 12 and 13 which are electrically connected in parallel. The total output of the cell array is connected to a load L.
In such a cell array, when some solar cells are shaded while all the remaining solar cells are irradiated with light, a reverse bias voltage is applied to the shaded solar cells. When the reverse bias voltage is large, the shaded cells are sometimes damaged, reducing the electric power generating ability of the cell array. A by-pass diode may be provided for passing a current in a direction opposite that of the output current of the submodules 30 in order to prevent the adverse effects caused by the reverse bias.
Referring to FIGS. 2A and 2B, submodules 30 are shown having one or more by-pass diodes. In FIG. 2A, one by-pass diode D is provided for one submodule 30 while by-pass diodes D.sub.1, D.sub.2, D.sub.3, and D.sub.4 are provided for solar cells 10, 11, 12, and 13, respectively, in FIG. 2B. Conventionally, these by-pass diodes are formed separately from the solar cells and are connected to the solar cells by wiring.
FIG. 3 illustrates a technique in which a by-pass diode is formed using the same semiconductor substrate on which the solar cell is formed. In the solar cell of FIG. 3, an n-type front diffusion layer 21 is formed on the front surface of a p-type silicon substrate 20 and a front electrode 24 is formed on a part thereof. Light is received through front diffusion layer 21, and electric power is generated by the effect of the pn junction formed at the interface of n-type layer 21 and p-type substrate 20. An n-type back diffusion layer 22 is formed by mesa-etching, and an electrode 23 for the by-pass diode is formed thereon. A back electrode (not shown) to be connected to another adjacent cell is further formed on a part of the back surface of silicon substrate 20.
Referring to FIG. 4, there is shown an equivalent circuit diagram of the solar cell in FIG. 3. As seen from this diagram, the positive potential side of a solar cell SC is connected to the negative potential side of a by-pass diode BD. The negative potential side of solar cell SC and the positive potential side of by-pass diode BD are open.
In the perspective view of FIG. 5A, three solar cells are connected in series. The negative side of a first cell 1 is connected to the positive side of a second cell 2 by a lead 25 and, similarly, the negative side of the second cell 2 is connected to the positive side of a third cell 3 by another lead 25. Leads 27, 28 on both ends are connected to a load (not shown). The positive side of the first cell 1 is connected to a back diffusion layer 22 on the back surface of the second cell by a lead 26, and similarly, the positive side of the second cell 2 is connected to back diffusion layer 22 of the third cell 3 by a lead 26.
Referring to FIG. 5B, there is shown an equivalent circuit diagram of the solar cells connected in series in FIG. 5A. That is, a by-pass diode A including n-type back diffusion layer 22 and a p-type silicon substrate 20 in the second cell 2 serves as a by-pass for the first cell 1 and a by-pass diode B on the third cell serves as a by-pass for the second cell. Accordingly, for the third cell 3, a separate diode C must be connected in parallel with the third cell 3.
Two leads 25, 26 are required between adjacent cells in a cell array including a plurality of solar cells having three terminals. The process for connecting an individual diode C to a solar cell is also complicated, increasing the manufacturing cost. Furthermore, in some cases, the individual diode C, and wires for connecting the same to a cell, project from the level of the main surface of the cell. Such projection of diode C and its connecting wires is not preferable in a cell array which must be folded, such as a solar cell array used in space.
A solar cell is available including an integrated by-pass diode and having only two terminals, as shown in FIG. 6, so as to overcome the difficulties in a cell array including cells having three terminals, as stated above. In the cell of FIG. 6, a p.sup.+ layer 41 is formed on the back surface of a p-type silicon substrate 40, which is covered with a back electrode 46. An n layer 42 is formed over a considerable portion of the front surface of silicon substrate 40, which is covered with an anti-reflection film 45. Light is received through n layer 42.
An n-type well 48 is formed in another portion of the front surface of substrate 40 and a p layer 49 is formed in a surface portion thereof. The portion of the front surface of substrate 40 except n layer 42 is covered with a SiO.sub.2 film 44. One end of a comb-shaped front electrode 43 connected to n layer 42 and formed on SiO.sub.2 film 44 is connected to p layer 49 through a contact hole made in SiO.sub.2 film 44. The junction between an n-type well 48 and the p-type silicon substrate 40 is short-circuited by a short-circuit electrode 47 through another contact hole formed in SiO.sub.2 film 44.
Referring to FIG. 7, there is shown an equivalent circuit diagram of the solar cell of FIG. 6. The solar cell SC in this figure includes p substrate 40 and n layer 42 in FIG. 6 and has two terminals 67, 68. A by-pass diode BD having a polarity opposite to that of solar cell SC and a parasitic diode DSC having the same polarity as that of cell SC are connected in series and in parallel with solar cell SC between terminals 67, 68. Parasitic diode DSC, however, is short-circuited.
By-pass diode BD includes n well 48 and p layer 49 in FIG. 6. Parasitic diode DSC includes p substrate 40 and n well 48 in FIG. 6 and is short-circuited by short-circuit electrode 47. That is, when a reverse bias voltage is applied to solar cell SC, the pn junction of by-pass diode BD is in the forward direction with respect to the reverse bias voltage and functions to release the reverse bias voltage between terminals 67, 68.
Also in the solar cell of FIG. 6, however, there are problems as follows. First, if the by-pass diode is located in the corner portion of the solar cell and the corner portion is mechanically damaged, the by-pass diode is disabled. Additionally, the heat generated when the current flows through the by-pass diode cannot be efficiently released. In some cases, the surface region (indicated by an arrow (a) in FIG. 6) of p-substrate 40 between n-well 48 for the by-pass diode and n-layer 42 for the solar cell is inverted to the n-type, degrading its electric characteristics.
Moreover, in some cases, n layer 42 for receiving incident light and p substrate 40 are short-circuited by front electrode 43 a the point indicated by an arrow (b) in FIG. 6, thereby degrading the electric characteristics. Though it is possible to carry out an insulation treatment by forming a CVD oxide film or a thermal oxide film in the vicinity of the point indicated by the arrow (b) in order to prevent the short-circuit, such an insulation treatment increases the manufacturing cost. Additionally, if the area of short-circuit electrode 47 is small, it degrades the forward direction characteristics of by-pass diode BD. Accordingly, when the current flows in by-pass diode BD, the heat generated by the current becomes large, resulting in the solar battery cell being damaged by the generated heat as well as increasing the amount of electric power lost.